Many products need various amounts of memory. Two of the most useful types of memory are high speed, low cost memory typically implemented as Dynamic Random Access Memory (DRAM) and non-volatile memory typically implemented as Electrically Erasable and Programmable Read Only Memory (EEPROM) or Flash memory. The ability to combine DRAM and EEPROM styles of memory, as well as logic and data processing functions implemented by Programmable Logic Arrays (PLA's) especially if little or no additional manufacturing complexity is required, would allow a number of cost effective applications that do not currently exist or that, heretofore were too costly to be commercially viable.
With the increasing array density of successive generations of DRAM chips, the attractiveness of merging other functions onto the chip also increases. However, any successful merged technology product must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing DRAM technology in order to provide added functions such as high speed logic, SRAM or EEPROM becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield. Thus, there is a need for a means of providing additional functions on a DRAM chip with little or no modification of the DRAM optimized process flow.
Among the desired additional functions, EEPROM is one for which the differences between the separately optimized technologies is the greatest. The typical EEPROM cell consists of a MOSFET with two stacked gates, a floating gate directly over the device channel and a control gate atop and capacitively coupled to it.
It would be very desirable to reduce all the major elements of a PC on to a single chip, including CPU, memory and input/output. While at the present time it may not be possible to make a whole PC on a single die, many processor like functions might most conveniently be embedded on the DRAM die. PLAs on a DRAM die would be well suited for memory address correction/repair by changing the addresses to remove faulty rows/columns, and replace them with functional ones. An example of a redundancy repair scheme is shown in U.S. Pat. No. 5,324,681 issued Lowrey on Jun. 28, 1994. Another is provided in U.S. Pat. No. 4,051,354 issued Choate on Sep. 27, 1997. Another is provide in U.S. Pat. No. 5,327,380 issued Kersh III on Jul. 5, 1994. None of these, however, incorporate an optimized DRAM technology process flow. PLAs on a DRAM die would also be desirable for use as dedicated processors embedded on the DRAM chip.
Recent publications outline the problems in trying to embed DRAMs in high performance ULSI logic. The conclusions are that because of the height differences between conventional stacked capacitor DRAM cells and high performance logic circuits that this can only be reasonably accomplished with trench capacitor DRAMS.
Modern DRAM technologies are driven by market forces and technology limitations to converge upon a high degree of commonality in basic cell structure. For the DRAM technology generations from 4 Mbit through 1 Gbit, the cell technology has converged into two basic structural alternatives; trench capacitor and stacked capacitor. A method for utilizing a trench DRAM capacitor technology to provide a compatible EEPROM cell has been described in U.S. Pat. No. 5,598,367. A different approach is needed for stacked capacitors however.
Thus, there is a need for merging processor and memory functions on a single DRAM chip. Similarly, there is a need for using PLAs on a DRAM chip as decoder devices. It is desirable that such processor/PLA capability be fabricated onto the DRAM chip with little or no modification of the DRAM optimized process flow.